This individual will be responsible for the development of analog or mixed-signal CMOS IP that will be integrated into via-configurable arrays.
Tasks/responsibilities include: analog transistor/gate level design and simulation, behavioral modeling of IP, physical layout/verification, and lab evaluation.
Requirements
- 6+ years experience in IC Design (4+ years with advanced degree, e.g. MSEE)
- Self motivated—requiring minimal supervision
- Excellent verbal and written communication skills.
- Theoretical and practical understanding of analog circuit design
- U.S. Citizen or Green Card holder
Preferences
- MSEE degree
- Physical layout experience
- Wide breadth of analog block design
- Background in Verilog-A
- Verilog/VHDL coding experience
